1. Field of the Invention
The invention relates to semiconductor technology and in particular to a semiconductor wafer with an assisting dicing structure and a dicing method thereof capable of preventing cracks from forming or propagating in the integrated circuits of the wafer during dicing.
2. Description of the Related Art
In the manufacture of microelectronic devices, a plurality of integrated circuits are formed on a semiconductor wafer, usually comprised primarily of silicon, by conventional semiconductor fabrication techniques, such as photolithography, film deposition and etching, and material doping. Thus, a semiconductor wafer can comprise a plurality of integrated circuits formed on a surface area of the wafer and arranged in rows and columns with the periphery of each integrated circuit being rectangular.
Typically, individual integrated circuits are formed by sawing or dicing through the wafer into rectangular discrete chips or diced along two mutually perpendicular sets of parallel lines or lanes referred to as dicing lines or lanes. Generally, elements or devices of the integrated circuit are not formed in the dicing lane regions, but dummy patterns for chemical mechanical polishing (CMP), test elements for testing the function elements, alignment marks for mask alignment or may be formed therein.
The sawing process is employed with a dicing blade coupled to a rotating spindle connected to a motor. The rotating spindle rotates at a high speed to cut the wafer into individual chips. However, stress may be created in the dicing lane regions during the sawing process. The created stress is a source of crack propagating into integrated circuit regions causing fatal defects. The cracking may be aggravated as the device material properties become weaker to meet various electrical property requirements.
Thus, there exists a need for an improved dicing method for a semiconductor wafer to reduce formation or propagation of cracks therein.